Semiconductor devices with through via electrodes, methods of fabricating the same, memory cards including the same, and electronic systems including the same

ABSTRACT

A semiconductor device includes a via electrode penetrating a substrate and a back-side molding layer covering a back-side surface of the substrate. The back-side molding layer contacts a sidewall of a back-side end portion of the via electrode, which is a portion of the via electrode that protrudes from the back-side surface of the substrate.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C 119(a) to KoreanApplication No. 10-2013-0097294, filed on Aug. 16, 2013, in the Koreanintellectual property Office, which is incorporated herein by referencein its entirety as set forth in full.

BACKGROUND

1. Technical Field

Embodiments of the present disclosure relate to semiconductor devicesand, more particularly, to semiconductor devices with through viaelectrodes, methods of fabricating the same, memory cards including thesame and electronic systems including the same.

2. Related Art

Semiconductor devices employed in electronic systems may include variouselectronic circuit elements. Electronic circuit elements may beintegrated in and/or on a semiconductor substrate to form asemiconductor device (also, referred to as a semiconductor chip or asemiconductor die). Semiconductor memory chips may also be employed inelectronic systems. Before semiconductor devices, includingsemiconductor memory chips, are employed in an electronic system, thesemiconductor devices may be encapsulated to form a package. Thesesemiconductor packages may be employed in the electronic systems, forexample, computers, mobile systems or data storage media.

As electronic systems such as mobile systems, which include smartphones, become lighter and smaller, the semiconductor packages employedin the mobile systems are increasingly scaled down. Thus, stackpackages, each of which includes a plurality of stacked semiconductorchips, are increasingly in demand with the development ofmulti-functional and high capacity semiconductor packages. In thisregard, there have been efforts to reduce the thickness and the size ofthe stack packages to provide thin and small stack packages. Inaddition, through silicon via (TSV) electrodes penetrating thesemiconductor chips have been proposed to realize interconnectionstructures that electrically couple the semiconductor chips to anexternal device.

SUMMARY

Various embodiments are directed to semiconductor devices with throughvia electrodes, methods of fabricating the same, memory cards includingthe same, and electronic systems including the same.

According to some embodiments, a semiconductor device includes a firstsubstrate, a first conductive via electrode extending from a front sidesurface of the first substrate toward a backside surface of the firstsubstrate to penetrate the first substrate, and a first backside moldinglayer covering the backside surface of the first substrate andcontacting sidewall of a backside end portion of the first conductivevia electrode. The first backside molding layer exposes a top surface ofthe backside end portion of the first conductive via electrode.

According to further embodiments, a semiconductor device includes afirst chip, a second chip, and a package molding layer. The first chipincludes a first substrate, a first conductive via electrode extendingfrom a front side surface of the first substrate toward a backsidesurface of the first substrate to penetrate the first substrate, and afirst backside molding layer covering the backside surface of the firstsubstrate and contacting a sidewall of a backside end portion of thefirst conductive via electrode. The second chip includes a secondsubstrate, a second conductive via electrode extending from a front sidesurface of the second substrate toward a backside surface of the secondsubstrate to penetrate the second substrate, and a second backsidemolding layer covering the backside surface of the second substrate andcontacting a sidewall of a backside end portion of the second conductivevia electrode. The second chip is stacked on the first chip such thatthe second conductive via electrode is electrically connected to thefirst conductive via electrode. The package molding layer coverssidewalls of the first and second chips and contacts the first andsecond backside molding layers.

According to further embodiments, a method of fabricating asemiconductor device includes forming a conductive via electrodeextending from a front side surface of the substrate toward a backsidesurface of the substrate to penetrate the substrate. The conductive viaelectrode is formed to include a backside end portion that protrudesfrom the backside surface of the substrate. An initial backside moldinglayer is formed on the backside surface of the substrate to cover theprotruded backside end portion of the conductive via electrode. Theinitial backside molding layer is ground to form a backside moldinglayer exposing the backside end portion of the conductive via electrode.

According to further embodiments, a memory card includes a semiconductordevice. The semiconductor device includes a first substrate, a firstconductive via electrode extending from a front side surface of thefirst substrate toward a backside surface of the first substrate topenetrate the first substrate, and a first backside molding layercovering the backside surface of the first substrate and contactingsidewall of a backside end portion of the first conductive viaelectrode. The first backside molding layer exposes a top surface of thebackside end portion of the first conductive via electrode.

According to further embodiments, a memory card includes a semiconductordevice. The semiconductor device includes a first chip, a second chip,and a package molding layer. The first chip includes a first substrate,a first conductive via electrode extending from a front side surface ofthe first substrate toward a backside surface of the first substrate topenetrate the first substrate, and a first backside molding layercovering the backside surface of the first substrate and contacting asidewall of a backside end portion of the first conductive viaelectrode. The second chip includes a second substrate, a secondconductive via electrode extending from a front side surface of thesecond substrate toward a backside surface of the second substrate topenetrate the second substrate, and a second backside molding layercovering the backside surface of the second substrate and contacting asidewall of a backside end portion of the second conductive viaelectrode. The second chip is stacked on the first chip such that thesecond conductive via electrode is electrically connected to the firstconductive via electrode. The package molding layer covers sidewalls ofthe first and second chips and contacts the first and second backsidemolding layers.

According to further embodiments, an electronic system includes asemiconductor device. The semiconductor device includes a firstsubstrate, a first conductive via electrode extending from a front sidesurface of the first substrate toward a backside surface of the firstsubstrate to penetrate the first substrate, and a first backside moldinglayer covering the backside surface of the first substrate andcontacting sidewall of a backside end portion of the first conductivevia electrode. The first backside molding layer exposes a top surface ofthe backside end portion of the first conductive via electrode.

According to further embodiments, an electronic system includes asemiconductor device. The semiconductor device includes a first chip, asecond chip, and a package molding layer. The first chip includes afirst substrate, a first conductive via electrode extending from a frontside surface of the first substrate toward a backside surface of thefirst substrate to penetrate the first substrate, and a first backsidemolding layer covering the backside surface of the first substrate andcontacting a sidewall of a backside end portion of the first conductivevia electrode. The second chip includes a second substrate, a secondconductive via electrode extending from a front side surface of thesecond substrate toward a backside surface of the second substrate topenetrate the second substrate, and a second backside molding layercovering the backside surface of the second substrate and contacting asidewall of a backside end portion of the second conductive viaelectrode. The second chip is stacked on the first chip such that thesecond conductive via electrode is electrically connected to the firstconductive via electrode. The package molding layer covers sidewalls ofthe first and second chips and contacts the first and second backsidemolding layers.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will become more apparent in viewof the attached drawings and accompanying detailed description, inwhich:

FIG. 1 is a cross-sectional view illustrating a semiconductor deviceaccording to an embodiment of the present invention;

FIGS. 2 to 5 are cross-sectional views illustrating a method offabricating a semiconductor device according to an embodiment of thepresent invention;

FIG. 6 is a cross-sectional view illustrating a semiconductor deviceaccording to another embodiment of the present invention;

FIG. 7 is a block diagram illustrating an electronic system including asemiconductor device according to an embodiment of the presentinvention; and

FIG. 8 is a block diagram illustrating another electronic systemincluding a semiconductor device according to an embodiment of thepresent invention.

DETAILED DESCRIPTION OF EMBODIMENTS

Embodiments of the present invention provide semiconductor devicesincluding via electrodes and methods of fabricating the same. Asemiconductor device according to an embodiment may include a back-sidemolding layer disposed on a back-side surface of a semiconductorsubstrate, which is exposed together with back-side end portions of viaelectrodes penetrating the semiconductor substrate. Thus, the back-sidemolding layer may prevent the back-side end portions of the viaelectrodes on the back side of the substrate from being damaged. Theback-side molding layer may include substantially the same material as apackage molding layer that protects sidewalls of a semiconductor chipincluding the semiconductor substrate. Accordingly, the back-sidemolding layer may prevent the package molding layer from peeling offfrom the semiconductor chip. As a result, a package failure is avoided.

It will be understood that although the terms first, second, third etc.may be used herein to describe various elements, these elements shouldnot be limited by these terms. These terms are only used to distinguishone element from another element. Thus, a first element in someembodiments could be termed a second element in other embodimentswithout departing from the teachings of the present invention.

It will also be understood that when an element is referred to as being“on”, “above”, “below”, or “under” another element, it can be directly“on”, “above”, “below”, or “under” the other element, respectively, orintervening elements may also be present. Accordingly, the terms such as“on”, “above”, “below”, or “under” which are used herein are for thepurpose of describing particular embodiments only and are not intendedto be limiting.

It will be further understood that when an element is referred to asbeing “connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Other words used to describe therelationship between elements or layers should be interpreted in asimilar fashion. The semiconductor substrate may have an active layercorresponding to a region where transistors and internal interconnectionlines constituting electronic circuits are integrated, and semiconductorchips may be obtained by separating the semiconductor substrate into aplurality of pieces.

The semiconductor chips may correspond to memory chips or logic chips.The memory chips may include dynamic random access memory (DRAM)circuits, static random access memory (SRAM) circuits, flash memorycircuits, magnetic random access memory (MRAM) circuits, resistiverandom access memory (ReRAM) circuits, ferroelectric random accessmemory (FeRAM) circuits, or phase change random access memory (PCRAM)circuits, which are integrated on and/or in the semiconductor substrate.The logic chips may include logic circuits which are integrated onand/or in the semiconductor substrate. In some cases, the term“semiconductor substrate” used herein may be construed as asemiconductor chip or a semiconductor die in which integrated circuitsare formed.

FIG. 1 illustrates a semiconductor device according to an embodiment.The semiconductor device includes via electrodes 200 that extend from afront-side surface 101 of a semiconductor substrate 100 toward aback-side surface 104 of the semiconductor substrate 100. That is, thevia electrodes 200 may vertically penetrate the semiconductor substrate100. The semiconductor substrate 100 may be a silicon substrate and mayhave a wafer form or a separate chip form. The front-side surface 101 ofthe semiconductor substrate 100 may correspond to a surface of an activelayer where integrated circuits are formed. The back-side surface 104 ofthe semiconductor substrate 100 may be a surface opposite to thefront-side surface 101 with respect to the body of the semiconductorsubstrate 100. Circuit elements such as transistors 110 constituting anintegrated circuit may be formed in and on the active layer, and adielectric layer 130 and internal interconnection structures 140 formedin the dielectric layer 130 may be disposed over the front-side surface101.

Each of the internal interconnection structures 140 may include aninterconnection line and a connection via to provide an electricalconnection structure. The internal interconnection structures 140electrically couple the via electrodes 200 to corresponding connectionpads 150. First conductive bumps 160 are disposed on correspondingconnection pads 150 to act as outer connection terminals for connectingthe semiconductor device to an external device. Thus, the firstconductive bumps 160 are electrically coupled to the corresponding viaelectrodes 200.

A passivation layer 170 is disposed on a surface of the dielectric layer130 to expose the connection pads 150. As illustrated in FIG. 1, the viaelectrodes 200 are electrically coupled to the first conductive bumps160 through the internal interconnection structures 140 and theconnection pads 150.

In another embodiment, the via electrodes 200 are directly connected tothe first conductive bumps 160, or each via electrode 200 and itscorresponding first conductive bump 160 may constitute a unitary body.The first conductive bumps 160 may be formed of a metal material such asa copper (Cu) material.

Conductive adhesive layers 180 are disposed on corresponding firstconductive bumps 160. The conductive adhesive layers 180 may be providedto improve an adhesive strength between the first conductive bumps 160and external connection terminals. The conductive adhesive layers 180may be formed of a solder layer. An interfacial layer may be disposedbetween the first conductive bumps 160 and the conductive adhesivelayers 180. The interfacial layer may include a wetting layer such as anickel layer or an oxidation resistant material layer such as a goldlayer.

The via electrodes 200 may correspond to through via electrodes such asthrough silicon vias (TSVs) or through electrodes. The via electrodes200 may be formed of a metal material. The via electrodes 200 may beformed of a gallium (Ga) material, an indium (In) material, a tin (Sn)material, a silver (Ag) material, a copper (Cu) material, a mercury (Hg)material, a bismuth (Bi) material, a lead (Pb) material, a gold (Au)material, a zinc (Zn) material, an aluminum (Al) material, or an alloythereof.

Back-side end portions 210 of the via electrodes 200 may protrude fromthe back-side surface 104 of the semiconductor substrate 100. In anembodiment, the back-side end portions 210 of the via electrodes 200penetrate a back-side molding layer 301 that is formed on the back-sidesurface 104 to protect the back-side surface 104 of the semiconductorsubstrate 100. That is, the back-side molding layer 301 may surroundsidewalls of the back-side end portions 210 of the via electrodes 200 toelectrically insulate the back-side end portions 210 from each other.

The back-side molding layer 301 may be formed by performing a back-sidemolding process for covering the back-side surface 104 of thesemiconductor substrate 100 with an epoxy molding compound (EMC)material. Thus, the back-side molding layer 301 can be formed at a lowcost. Furthermore, the back-side molding layer 301 may be more solid andharder than an oxide layer or a polyimide layer that is used as aback-side passivation layer. Thus, the back-side molding layer 301 mayprevent the back-side end portions 210 of the via electrodes 200 frombeing deformed during a grinding process for exposing the back-side endportions 210 of the via electrodes 200.

The back-side end portions 210 of the via electrodes 200 are coveredwith second conductive bumps 360 acting as outer connection terminals.The second conductive bumps 360 may be formed of a metal material suchas a copper material. The first conductive bumps 160 disposed on thefront-side surface 101 of the semiconductor substrate 100 areelectrically coupled to the second conductive bumps 360 disposed on theback-side surface 104 of the semiconductor substrate 100 through the viaelectrodes 200.

FIGS. 2 to 5 are cross-sectional views illustrating a method offabricating the semiconductor device shown in FIG. 1 according to anembodiment of the present invention.

Referring to FIG. 2, a plurality of transistors 110 are formed in anactive layer which is adjacent to a front-side surface 101 of asemiconductor substrate 100. An interlayer insulation layer 120 isformed on the front-side surface 101 of the semiconductor substrate 100to cover the transistors 110. After that, via electrodes 200 are formedto penetrate the interlayer insulation layer 120 and to extend into thesemiconductor substrate 100. That is, the via electrodes 200 are formedto extend from the front-side surface 101 of the semiconductor substrate100 toward an initial back-side surface 103 of the semiconductorsubstrate 100.

The via electrodes 200 may be formed using a process of forming throughsilicon vias (TSVs) at a wafer level. In particular, the interlayerinsulation layer 120 and the semiconductor substrate 100 are etched toform via holes 205 that have openings at the front-side surface 101 andextend toward the initial back-side surface 103. A conductive materialsuch as a copper material then fills the via holes 205. As a result, thevia electrodes 200 are formed in each one of the via holes 205.

The via holes 205 may be formed to have different depths from each otherdepending on their locations in the semiconductor substrate 100. Thus,the via electrodes 200 may also be formed to have different verticallengths according to their locations in the semiconductor substrate 100.In FIG. 2, the via electrodes 200 include relatively short viaelectrodes 201 and relatively long via electrodes 203. Although notshown in the drawings, an insulation liner may be formed between the viaelectrodes 200 and the semiconductor substrate 100.

Subsequently, a dielectric layer 130 and internal interconnectionstructures 140 disposed in the dielectric layer 130 are formed on theinterlayer insulation layer 120 and the via electrodes 200. Connectionpads 150 are formed in an upper portion of the dielectric layer 130 tobe coupled to corresponding internal interconnection structures 140.

A passivation layer 170 for exposing part of the connection pads 150 isformed on the dielectric layer 130 and the connection pads 150. Afterthat, first conductive bumps 160 are formed on each of the exposedconnection pads 150. Conductive adhesive layers 180 are formed on eachof the first conductive bumps 160. The processes described above may beperformed while the semiconductor substrate 100 is oriented such thatthe initial back-side surface 103 is provided as the bottom surface ofthe substrate 100 and the front-side surface 101 is provided as the topsurface of the substrate 100. After forming the conductive adhesivelayers 180 over the semiconductor substrate 100, the semiconductorsubstrate 100 is turned over so that the initial back-side surface 103of the semiconductor substrate 100 is provided as the top of thesubstrate 100 and the front-side surface 101 is provided as the bottomsurface of the substrate 100, as shown in FIG. 2.

Referring to FIG. 3, a process for removing a portion of the back sideof the semiconductor substrate 100 by a predetermined thickness R isperformed on the initial back-side surface 103 to expose back-side endportions 210 of the via electrodes 200. The process for removing theportion of the back side of the semiconductor substrate 100 may be a dryetch process such that the back-side end portions 210 of the viaelectrodes 200 protrude from a back-side surface 104 of the etchedsemiconductor substrate 100. In an embodiment, since the via electrodes200 are formed to have different vertical lengths depending on theirlocations in the semiconductor substrate 100, lengths of the back-sideend portions 210 protruding from the back-side surface 104 may also bedifferent from each other.

Referring to FIG. 4, an initial back-side molding layer 300 is formed tocover the back-side surface 104 of the semiconductor substrate 100 andthe back-side end portions 210 of the via electrodes 200. The initialback-side molding layer 300 may be formed at a wafer level using amolding apparatus. The initial back-side molding layer 300 may be formedof an epoxy molding compound (EMC) material. The initial back-sidemolding layer 300 may be formed to have a sufficient thickness to coverthe back-side end portions 210 of the via electrodes 200.

In an embodiment, the initial back-side molding layer 300 is formed tohave a thickness of about 100 micrometers to about 150 micrometers.Since the initial back-side molding layer 300 is formed using themolding apparatus, a surface of the initial back-side molding layer 300may have a flat, even profile rather than an uneven profile. The initialback-side molding layer 300 may be formed of an EMC material which isrelatively harder than an oxide layer or a polyimide layer. Thus, theinitial back-side molding layer 300 may reinforce the original shapes ofthe top surfaces of the back-side end portions 210′ (see FIG. 5) of thevia electrodes 200 even though the initial back-side molding layer 300and the vertical length of the back-side end portions 210 are ground ina subsequent process. That is, the initial back-side molding layer 300may prevent the back-side end portions 210 of the via electrodes 200from being deformed or broken during a grinding process that isperformed to expose the back-side end portions 210 of the via electrodes200.

Referring to FIG. 5, the initial back-side molding layer 300 and theback-side end portions 210 are ground to form a back-side molding layer301 that exposes top surfaces 209 of ground back-side end portions 210′of the via electrodes 200. The grinding process is indicated by “G” inFIG. 5. After the initial back-side molding layer 300 is ground in thegrinding process G, a top surface of the back-side molding layer 301 maybe substantially flat. The back-side end portions 210 of the viaelectrodes 200 are partially removed during the back grinding process G.As a result, the via electrodes 200 have substantially the same lengthafter the back grinding process G is performed.

As described above, since the initial back-side molding layer 300 may beformed of the EMC material, the initial back-side molding layer 300 mayprevent the top surfaces of the back-side end portions 210′ of the viaelectrodes 200 from being deformed or broken during the back grindingprocess G. In an embodiment, the initial back-side molding layer 300 andthe back-side end portions 210 may be planarized using a chemicalmechanical polishing (CMP) process instead of the grinding process G.

After performing the grinding process G, second conductive bumps (360 ofFIG. 1) may be formed on each of the ground back-side end portions 210′of the via electrodes 200.

After the via electrodes 200 penetrating the semiconductor substrate 100are formed at a wafer level, the semiconductor substrate 100 may beseparated into a plurality of semiconductor chips using a die sawingprocess. Then, at least two semiconductor chips may be stacked to form astack package. Alternatively, after the via electrodes 200 penetratingthe semiconductor substrate 100 are formed at a wafer level, a pluralityof semiconductor substrates 100 may be stacked at a wafer level, andthen the plurality of stacked semiconductor substrates 100 may be cutusing a die sawing process to form a plurality of stack packages. As aresult, semiconductor devices are formed as stack packages.

FIG. 6 is a cross-sectional view illustrating a semiconductor deviceaccording to another embodiment of the present invention.

Referring to FIG. 6, the semiconductor device has a stack package formin which a plurality of semiconductor chips 1000, 2000, 3000, 4000, and5000 is stacked. An underfill layer (or an insulating layer or anadhesive layer) may be interposed between the stacked chips. At leastone of the semiconductor chips 1000, 2000, 3000, 4000, and 5000 includesa semiconductor substrate 100 and via electrodes 200 penetrating thesemiconductor substrate 100. In FIG. 6, the same reference numerals asused in FIGS. 1 to 5 are used to denote the same elements as in FIGS. 1to 5.

The semiconductor device includes the first semiconductor chip 1000, thesecond semiconductor chip 2000 stacked on the first semiconductor chip1000, and a package molding layer 400 covering sidewalls of the firstand second semiconductor chips 1000 and 2000. The package molding layer400 may act as a protective layer. In an embodiment, the first andsecond semiconductor chips 1000 and 2000 are configured to have the sameintegrated circuit that executes substantially the same function. Inanother embodiment, the first and second semiconductor chips 1000 and2000 are configured to have different integrated circuits that executedifferent functions.

The first semiconductor chip 1000 includes a first semiconductorsubstrate 1100, a plurality of first via electrodes 1200 penetrating thefirst semiconductor substrate 1100, and a first back-side molding layer1301 covering a back-side surface of the first semiconductor substrate1100 and surrounding external surfaces of sidewalls of back-side endportions of the first via electrodes 1200. The first back-side moldinglayer 1301 may be formed to expose top surfaces of the back-side endportions of the first via electrodes 1200. The first back-side moldinglayer 1301 may be formed by molding an epoxy molding compound (EMC)material.

The second semiconductor chip 2000 may have substantially the sameconfiguration as the first semiconductor chip 1000. That is, the secondsemiconductor chip 2000 includes a second semiconductor substrate 2100,a plurality of second via electrodes 2200 penetrating the secondsemiconductor substrate 2100, and a second back-side molding layer 2301covering a back-side surface of the second semiconductor substrate 2100and surrounding external surfaces of sidewalls of back-side end portionsof the second via electrodes 2200. The second back-side molding layer2301 may be formed to expose top surfaces of the back-side end portionsof the second via electrodes 2200. The second back-side molding layer2301 may be formed by molding the EMC material. The second semiconductorchip 2000 is stacked on the first semiconductor chip 1000 such that thesecond via electrodes 2200 are electrically coupled to the first viaelectrodes 1200.

The package molding layer 400 may function as a protective layer thatprotects the first and second semiconductor chips 1000 and 2000. Thepackage molding layer 400 may be formed of substantially the samematerial as the first and second back-side molding layers 1301 and 2301.The package molding layer 400 may be formed by molding the EMC material.Since the package molding layer 400, the first back-side molding layer1301, and the second back-side molding layer 2301 are formed ofsubstantially the same material, adhesion between the package moldinglayer 400 and the first and second back-side molding layers 1301 and2301 may be improved.

The package molding layer may be attached to only sidewalls of a stackedstructure including the first and second semiconductor substrates toconstitute a conventional stacked package having a fan-out package form.In such a case, because the package molding layer is attached to onlythe sidewalls of the stacked structure, an adhesive strength between thestacked structure and the package molding layer may be degraded.

However, according to an embodiment, the first back-side molding layer1301 formed of the same material as the package molding layer 400 isdisposed between the first and second semiconductor chips 1000 and 2000.In addition, a back-side surface of the second semiconductor chip 2000is covered with the second back-side molding layer 2301 formed of thesame material as the package molding layer 400. Thus, the first andsecond back-side molding layers 1301 and 2301 may be strongly combinedwith the package molding layer 400 to prevent the package molding layer400 from being delaminated from the sidewalls of the stacked structure.

The third semiconductor chip 3000 may be additionally disposed on afront-side surface of the first semiconductor chip 1000. That is, thethird semiconductor chip 3000 is disposed opposite to the secondsemiconductor chip 2000 with respect to the first semiconductor chip1000. The third semiconductor chip 3000 includes a third semiconductorsubstrate 3100 and a plurality of third via electrodes 3200 penetratingthe third semiconductor substrate 3100. The third via electrodes 3200are electrically coupled to the first via electrodes 1200.

Third conductive bumps 3160 are disposed on a front-side surface of thethird semiconductor substrate 3100 that is opposite to the firstsemiconductor chip 1000. The third conductive bumps 3160 act as outerconnection terminals that electrically couple the stacked package toanother substrate or a mother board.

The third semiconductor chip 3000 may have a greater width than thefirst semiconductor chip 1000. Since the third semiconductor chip 3000is wider than the first semiconductor chip 1000, when the firstsemiconductor chip 1000 is mounted on a back-side surface of the thirdsemiconductor chip 3000, edges of the third semiconductor chip 3000 maylaterally extend beyond the sidewalls of the first semiconductor chip1000. The package molding layer 400 on the sidewalls of the firstsemiconductor chip 1000 may be flush with the edges of the thirdsemiconductor chip 3000. That is, the package molding layer 400 may bemolded such that outer sidewall surfaces of the package molding layer400 are vertically aligned with sidewall surfaces of the thirdsemiconductor chip 3000. In an embodiment, the third semiconductor chip3000 may be replaced with an interposer, a printed circuit board (PCB),or a dummy substrate, which provides only electrical interconnectionwithout any functions of a semiconductor chip.

The fourth semiconductor chip 4000 having substantially the sameconfiguration as the second semiconductor chip 2000 may be additionallystacked on a back-side surface of the second semiconductor chip 2000.Furthermore, the fifth semiconductor chip 5000 may be stacked on thefourth semiconductor chip 4000. The fifth semiconductor chip 5000 mayhave substantially the same function as the first or secondsemiconductor chip 1000 or 2000. Alternatively, the fifth semiconductorchip 5000 may have a different function from the first and secondsemiconductor chips 1000 and 2000.

In an embodiment, the fifth semiconductor chip 5000 corresponding to atopmost semiconductor chip may not include the via electrodes asillustrated in FIG. 6. In another embodiment, the fifth semiconductorchip 5000 may include via electrodes that are substantially the same asthose of the first or second semiconductor chip 1000 or 2000. Thepackage molding layer 400 may extend to cover and protect sidewalls ofthe fourth and fifth semiconductor chips 4000 and 5000. A top surface5001 of the fifth semiconductor chip 5000 that is on an opposite side toa side attached to the fourth semiconductor chip 4000 may be exposed toenhance heat radiation efficiency of the stacked package.

FIG. 7 is a block diagram illustrating an electronic system including asemiconductor device according to an embodiment of the presentinvention. The semiconductor device is provided in the form of a memorycard 1800. The memory card 1800 includes a memory 1810 and a memorycontroller 1820.

The memory 1810 may include at least one of nonvolatile memory devicesto which the packaging technology according to an embodiment of thepresent invention is applied. The memory controller 1820 may controloperations for storing data in the memory 1810 and reading out datastored in the memory 1810 in response to a read/write request from ahost 1830.

FIG. 8 is a block diagram illustrating another electronic systemincluding a semiconductor device according to an embodiment of thepresent invention. The electronic system 2710 includes a controller2711, an input/output unit 2712, and a memory 2713. The controller 2711,the input/output unit 2712, and the memory 2713 are coupled with oneanother through a bus 2715 providing a path through which data moves.

The controller 2711 may include at least one of at least onemicroprocessor, at least one digital signal processor, at least onemicrocontroller, and logic devices capable of performing the samefunctions as these components. The controller 2711 or the memory 2713may include at least one semiconductor device according to an embodimentof the present invention. The input/output unit 2712 may include atleast one of a keypad, a keyboard, a display device, a touch screen, andso forth.

The memory 2713 may store data and/or commands to be executed by thecontroller 2711. The memory 2713 may include a volatile memory devicesuch as a DRAM and/or a nonvolatile memory device such as a flashmemory. The flash memory may be mounted to an information processingsystem such as a mobile terminal or a desk top computer. The flashmemory may constitute a solid state disk (SSD). In this case, theelectronic system 2710 may stably store a large amount of data in aflash memory system.

The electronic system 2710 may further include an interface 2714configured to transmit and receive data to and from a communicationnetwork. The interface 2714 may have a wired or wireless configuration.The interface 2714 may include an antenna or a wired or wirelesstransceiver.

The electronic system 2710 may be realized as a mobile system, apersonal computer, an industrial computer or a logic system performingvarious functions. The mobile system may be any one of a personaldigital assistant (PDA), a portable computer, a tablet computer, amobile phone, a smart phone, a wireless phone, a laptop computer, amemory card, a digital music system, and an informationtransmission/reception system.

When the electronic system 2710 is used as equipment capable ofperforming wireless communication, the electronic system 2710 may beused in a communication system such as one of CDMA (code divisionmultiple access), GSM (global system for mobile communications), NADC(north American digital cellular), E-TDMA (enhanced-time divisionmultiple access), WCDAM (wideband code division multiple access),CDMA2000, LTE (long term evolution), and Wibro (wireless broadbandInternet).

Embodiments of the present invention have been disclosed above forillustrative purposes. Those skilled in the art will appreciate thatvarious modifications, additions and substitutions are possible, withoutdeparting from the scope and spirit of the present invention asdisclosed in the accompanying claims.

What is claimed is:
 1. A semiconductor device comprising: a firstsubstrate; a first via electrode penetrating the first substrate andincluding a back-side end portion that protrudes from a back-sidesurface of the first substrate; a first back-side molding layer coveringthe back-side surface of the first substrate and surrounding surfaces ofa sidewall of the back-side end portion of the first via electrode; asecond substrate stacked over the first substrate and electricallycoupled to the first via electrode; and a package molding layer coveringsidewalls of the first and second substrates and a sidewall of the firstback-side molding layer, wherein the package molding layer is formed ofa material that is substantially the same as a material of the firstback-side molding layer.
 2. The semiconductor device of claim 1, whereinthe package molding layer covers the sidewalls of the first and secondsubstrates so that a back-side surface of the second substrate isexposed, and wherein a front-side surface of the second substrate facesthe back-side surface of the first substrate.
 3. The semiconductordevice of claim 1, wherein the package molding layer and the firstback-side molding layer are formed of an epoxy molding compoundmaterial.
 4. The semiconductor device of claim 1, further comprising: asecond via electrode penetrating the second substrate and electricallycoupled to the first via electrode, the second via electrode including aback-side end portion that protrudes from a back-side surface of thesecond substrate; and a second back-side molding layer covering theback-side surface of the second substrate and surrounding a surface of asidewall of the back-side end portion of the second via electrode,wherein the package molding layer covers a sidewall of the secondback-side molding layer.
 5. The semiconductor device of claim 1, furthercomprising: a third substrate disposed under the first substrate; athird via electrode penetrating the third substrate and electricallycoupled to the first via electrode, the third via electrode including aback-side end portion that protrudes from a back-side surface of thethird substrate; a third back-side molding layer covering the back-sidesurface of the third substrate and surrounding a surface of a sidewallof the back-side end portion of the third via electrode; an outerconnection terminal attached to a front-side surface of the thirdsubstrate and electrically coupled to the third via electrode; and apackage molding layer covering sidewalls of the first substrate and thefirst back-side molding layer and contacting an outer part of a topsurface of the third back-side molding layer.
 6. The semiconductordevice of claim 1, further comprising an interposer or a printed circuitboard over which the first substrate is stacked, wherein the interposeror the printed circuit board has a greater width than a width of thefirst substrate.
 7. A semiconductor device comprising: a plurality ofvertically stacked chips, wherein the plurality of vertically stackedchips comprises: a first chip including a first substrate, a first viaelectrode penetrating the first substrate, and a first back-side moldinglayer covering a back-side surface of the first substrate andsurrounding a surface of a sidewall of a first back-side end portion ofthe first via electrode, the first back-side end portion protruding fromthe back-side surface of the first substrate; a second chip including asecond substrate, a second via electrode penetrating the secondsubstrate, and a second back-side molding layer covering a back-sidesurface of the second substrate and surrounding a surface of a sidewallof a second back-side end portion of the second via electrode, thesecond back-side end portion protruding from the back-side surface ofthe second substrate; and a package molding layer covering sidewalls ofthe first and second chips and sidewalls of the first and secondback-side molding layers, wherein the second chip is stacked over thefirst chip such that the second via electrode is electrically coupled tothe first via electrode, and wherein the package molding layer is formedof a material that is substantially the same as a material of the firstand second back-side molding layers.
 8. The semiconductor device ofclaim 7, wherein the package molding layer and the first and secondback-side molding layers are formed with an epoxy molding compoundmaterial.
 9. The semiconductor device of claim 7, wherein the pluralityof chips further comprises a third chip under which the first chip isstacked, wherein the third chip has a greater width than the first chip.10. The semiconductor device of claim 9, wherein the third chip includesa third substrate, a third via electrode penetrating the thirdsubstrate, and a third back-side molding layer covering a back-sidesurface of the third substrate and surrounding a surface of a sidewallof a third back-side end portion of the third via electrode, the thirdback-side end portion protruding from the back-side surface of the thirdsubstrate.
 11. The semiconductor device of claim 7, further comprisingan interposer or a printed circuit board over which the first chip isstacked, wherein the interposer or the printed circuit board has agreater width than the first chip.